And at the end you have a suffix with 2 slow clock cycles. The suffix is really different, with 6 clock clocks but also a fast clock group in between. There are 3 major sections: For the cheap clone, the spacing is huge: The set of signals below that is a slightly zoomed in version of the one above.
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If we ignore for a second that the cheap clone doesn’t work on this particular board, the biggest consequence of the chapeau clone is that bulk transfers are much slower: All processing is done with a simply state machine.
For this investigation, it doesn’t matter what gets transported when, but it’s almost certain that the slow clock cycles are used to move the JTAG TAP from iDLE state to the scan Teeasic or scan IR state, and that the fast clock groups are used to rapidly scan data in and out of a scan data register.
As Glaster wrote earlierthe biggest issue with the cheap clone is that it doesn’t work on my eeColor Color3 board. We have a prefix with 8 slow clocks, but in between the second and the third slow clock, there’s a signal teasic clock group. But the cheap clone runs TCK at exactly double the speed of the Terasic, and both devices only use a flimsy, cheap flat cable. About Us Contact Hackaday.
The suffix is really different, with 6 clock clocks but also a fast clock group in between.
There are 3 major sections: For the cheap clone, the spacing is huge: The cheap clone was never able to get reliable contact. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today: My money is on the clock teradic Sign up Already a member? The Terasic doesn’t have that problem: What remains is the question about why the cheap clone doesn’t work.
It looks like the cheap clone is able to squeeze out bits blastter fast, but there’s quite a bit of software overhead in processing the next byte in the USB blastdr. A really interesting difference is in the spacing between fast clock groups: When you zoom in on the slow clock cycles, you can measure a TCK frequency of kHz: In the middle there are 16 groups with fast clock cycles each group is itself 8 clock cycles.
Terasic vs Cheap Clone USB Blaster
This is the first transaction that travels over the JTAG cable when you issue the “nios2-terminal” command. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today:.
A fast clock group sets the clock at 12MHz instead of 6MHz. Yes, delete it Cancel. We see a similar pattern, but interestingly enough, it’s not the same.
For the overview, look at the upper set. In the middle we have the expected 16 fast clock groups. And at the end you have a suffix with 2 slow clock cycles.
Terasic vs Cheap Clone USB Blaster | Details |
The most important signal here is TCK, in yellow. In addition, there are roughly 3 idle cycles between a fast clock group.
Zooming in on the slow clocks, we see a clock frequency of kHz. It’s blasteer that it’s broken: And here’s the equivalent of the cheap clone.
Terasic – Turnkey Solutions – Achievements – Altera USB Blaster Download Cable
It may be that 12MHz usv really just pushing things too much. The set of signals below that is a slightly zoomed in version of the one above.
While the Terasic was rock solid in its communication with the Color3 board. Meanwhile, during a fast clock group, the clock toggles at 6MHz.